With the scaling down of integrated circuit (IC) design, the leakage current imposes severe power problem for devices with IC. The power consumed by an integrated circuit can be categorized as dynamic, static and current leakage, respectively. The leakage current consumes the power and generates heat even when the circuit is not in operation; hence, minimizing the leakage current can alleviate both the power consumption and the heat dissipation problems.
U.S. Pat. No. 6,191,606 B1 (2001), “Method and apparatus for reducing standby leakage current using input vector activation” disclosed a method and an apparatus for reducing standby leakage current in CMOS circuit using selected input vectors. FIG. 1 shows the conceptual model of how an input vector can be used to turn off part of the circuit. When a normal clock Clk1 is applied to the input register 101, an input vector is applied to the combination logic circuit 103, which operates to generate an output vector. When a gated clock Clk2 is applied to the input vector, a pre-determined input vector is applied to the combinational logic circuit 103 to turn off part of the circuit to minimize the leakage current for reducing power consumption. However, the drawback of the patent is that the pre-determined input vector must be manually determined by visual inspection to the given logic circuit.
U.S. Pat. No. 6,515,513 B2 (2002) disclosed a system and method for inserting leakage reduction control in logic circuits. In this patent, a probabilistic analysis algorithm based on a user-defined probability is used to compute the input vector for leakage current reduction.
Step 302 in FIG. 3A is to select between the PMOS and the NMOS logic representations the one with deepest serial stack. The operation of step 302 is shown in FIG. 3b and further described as follows. Referring to FIG. 3b, the depths of the two sub-graphs WFP and WFN are first determined, respectively, as shown in step 302a. By performing a depth-first search (DFS) algorithm from the output terminal node to the Power Vdd and Ground Vss to find the longest path with most edges, i.e., the depth, traversed in each sub-graph. Step 302b is to determine whether the depth of sub-graph WFP is greater than or equals to the depth of sub-graph WFN. If so, the sub-graph WFP is used for the following weight assignment step, as illustrated in step 302c, i.e. WFT=WFP. Otherwise, WFN is used, as illustrated in step 302d, i.e. WFT=WFN. In other words, WFT is the maximum of WFP and WFN.
The leakage current of a TSMC 0.13 um CMOS 4-input NOR gate with respect to different inputs is measured and found to have the differences between maximum and minimum leakage currents of an order of two. Another observation is that the closer the off-state devices are to the output terminal, the lower the leakage current is. This phenomenon implies that an optimization factor based on the above observation can be used as a heuristic design to compute an optimal input vector for minimizing leakage current.